ALTERA EP22V10PC-25

Mounting Type

Through Hole

Package / Case

24-DIP

Surface Mount

having leads that are designed to be soldered on the side of a circuit board that the body of the component is mounted on.

NO

Supplier Device Package

24-PDIP

Number of Terminals

24

Package

Bulk

Number of Macrocells

10

Mfr

Altera

Product Status

Active

Package Description

DIP,

Package Style

IN-LINE

Moisture Sensitivity Levels

NOT SPECIFIED

Package Body Material

PLASTIC/EPOXY

Supply Voltage-Nom

5 V

Reflow Temperature-Max (s)

NOT SPECIFIED

Supply Voltage-Min

4.75 V

Operating Temperature-Max

70 °C

Rohs Code

No

Manufacturer Part Number

EP22V10PC-25

Clock Frequency-Max

35.7 MHz

Package Code

DIP

Package Shape

RECTANGULAR

Manufacturer

Rochester Electronics LLC

Part Life Cycle Code

Active

Number of I/O Lines

10

Ihs Manufacturer

ROCHESTER ELECTRONICS INC

Supply Voltage-Max

5.25 V

Risk Rank

5.78

Part Package Code

DIP

Series

-

JESD-609 Code

e0

Pbfree Code

No

Terminal Finish

TIN LEAD

Additional Feature

Any Feature, including a modified Existing Feature, that is not an Existing Feature.

MACROCELLS INTERCONNECTED BY GLOBAL BUS; 10 MACROCELLS; 1 EXTERNAL CLOCK

Technology

CMOS

Terminal Position

DUAL

Terminal Form

Occurring at or forming the end of a series, succession, or the like; closing; concluding.

THROUGH-HOLE

Peak Reflow Temperature (Cel)

NOT SPECIFIED

Terminal Pitch

The center distance from one pole to the next.

2.54 mm

Reach Compliance Code

unknown

Pin Count

a count of all of the component leads (or pins)

24

JESD-30 Code

R-PDIP-T24

Qualification Status

An indicator of formal certification of qualifications.

COMMERCIAL

Temperature Grade

Temperature grades represent a tire's resistance to heat and its ability to dissipate heat when tested under controlled laboratory test conditions.

COMMERCIAL

Programmable Type

These include Field Programmable Logic Devices (FPGAs), Complex Programmable Logic Devices (CPLD) and Programmable Logic Devices (PLD, PLA, PAL, GAL). There are also devices that are the analog equivalent of these called field programmable analog arrays.

EPLD

Speed

25 ns

Propagation Delay

the flight time of packets over the transmission link and is limited by the speed of light.

25 ns

Organization

11 DEDICATED INPUTS, 10 I/O

Seated Height-Max

4.32 mm

Programmable Logic Type

Generally, programmable logic devices can be described as being one of three different types: Simple programmable logic devices (SPLD) Complex programmable logic devices (CPLD) Field programmable logic devices (FPGA).

OT PLD

Output Function

An output function is a function that an optimization function calls at each iteration of its algorithm. Typically, you use an output function to generate graphical output, record the history of the data the algorithm generates, or halt the algorithm based on the data at the current iteration.

MACROCELL

Number of Dedicated Inputs

11

Width

7.62 mm

Length

31.68 mm