ALTERA EP220LC-7A

Package / Case

20-LCC (J-Lead)

Mounting Type

Surface Mount

Surface Mount

having leads that are designed to be soldered on the side of a circuit board that the body of the component is mounted on.

YES

Supplier Device Package

20-PLCC (9x9)

Number of Terminals

20

RoHS

Compliant

Product Status

Active

Mfr

Altera

Number of Macrocells

8

Package

Bulk

Package Description

QCCJ,

Package Style

CHIP CARRIER

Moisture Sensitivity Levels

NOT SPECIFIED

Package Body Material

PLASTIC/EPOXY

Supply Voltage-Nom

5 V

Reflow Temperature-Max (s)

30

Supply Voltage-Min

4.75 V

Operating Temperature-Max

70 °C

Rohs Code

No

Manufacturer Part Number

EP220LC-7A

Clock Frequency-Max

115 MHz

Package Code

QCCJ

Package Shape

SQUARE

Manufacturer

Rochester Electronics LLC

Part Life Cycle Code

Active

Number of I/O Lines

8

Ihs Manufacturer

ROCHESTER ELECTRONICS INC

Supply Voltage-Max

5.25 V

Risk Rank

5.84

Part Package Code

QLCC

Series

-

JESD-609 Code

e0

Pbfree Code

No

Terminal Finish

TIN LEAD

Additional Feature

Any Feature, including a modified Existing Feature, that is not an Existing Feature.

8 MACROCELLS

Terminal Position

QUAD

Terminal Form

Occurring at or forming the end of a series, succession, or the like; closing; concluding.

J BEND

Peak Reflow Temperature (Cel)

220

Terminal Pitch

The center distance from one pole to the next.

1.27 mm

Reach Compliance Code

unknown

Pin Count

a count of all of the component leads (or pins)

20

JESD-30 Code

S-PQCC-J20

Qualification Status

An indicator of formal certification of qualifications.

COMMERCIAL

Temperature Grade

Temperature grades represent a tire's resistance to heat and its ability to dissipate heat when tested under controlled laboratory test conditions.

COMMERCIAL

Programmable Type

These include Field Programmable Logic Devices (FPGAs), Complex Programmable Logic Devices (CPLD) and Programmable Logic Devices (PLD, PLA, PAL, GAL). There are also devices that are the analog equivalent of these called field programmable analog arrays.

EPLD

Speed

7.5 ns

Propagation Delay

the flight time of packets over the transmission link and is limited by the speed of light.

7.5 ns

Organization

9 DEDICATED INPUTS, 8 I/O

Seated Height-Max

4.572 mm

Programmable Logic Type

Generally, programmable logic devices can be described as being one of three different types: Simple programmable logic devices (SPLD) Complex programmable logic devices (CPLD) Field programmable logic devices (FPGA).

OT PLD

Number of Gates

The number of gates per IC varies depending on the number of inputs per gate. Two?input gates are common, but if only a single input is required, such as in the 744 NOT(or inverter) gates, a 14 pin IC can accommodate 6 (or Hex) gates.

300

Number of Logic Blocks (LABs)

8

Output Function

An output function is a function that an optimization function calls at each iteration of its algorithm. Typically, you use an output function to generate graphical output, record the history of the data the algorithm generates, or halt the algorithm based on the data at the current iteration.

MACROCELL

Number of Dedicated Inputs

9

Width

8.9662 mm

Length

8.9662 mm