GAL6002B15LP

Lattice Semiconductor GAL6002B15LP

Part No:

GAL6002B15LP

Datasheet:

-

Package:

-

AINNX NO:

35849245-GAL6002B15LP

Description:

Simple Programmable Logic Devices - SPLDs HI PERF E2CMOS FPLA

Products specifications
  • Surface Mount

    having leads that are designed to be soldered on the side of a circuit board that the body of the component is mounted on.

    NO
  • Number of Terminals
    24
  • Number of Macrocells
    38
  • RoHS
    Non-Compliant
  • Package Description
    PLASTIC, DIP-24
  • Package Style
    IN-LINE
  • Package Body Material
    PLASTIC/EPOXY
  • Package Equivalence Code
    DIP24,.3
  • Supply Voltage-Nom
    5 V
  • Supply Voltage-Min
    4.75 V
  • Operating Temperature-Max
    75 °C
  • Rohs Code
    No
  • Manufacturer Part Number
    GAL6002B-15LP
  • Clock Frequency-Max
    43.4 MHz
  • Package Code
    DIP
  • Package Shape
    RECTANGULAR
  • Manufacturer
    Lattice Semiconductor Corporation
  • Part Life Cycle Code
    Obsolete
  • Number of I/O Lines
    10
  • Ihs Manufacturer
    LATTICE SEMICONDUCTOR CORP
  • Supply Voltage-Max
    5.25 V
  • Risk Rank
    8.71
  • Part Package Code
    DIP
  • JESD-609 Code
    e0
  • ECCN Code
    EAR99
  • Terminal Finish
    Tin/Lead (Sn85Pb15)
  • Max Operating Temperature

    The Maximum Operating Temperature is the maximum body temperature at which the thermistor is designed to operate for extended periods of time with acceptable stability of its electrical characteristics.

    75 °C
  • Min Operating Temperature
    0 °C
  • Additional Feature

    Any Feature, including a modified Existing Feature, that is not an Existing Feature.

    REGISTER PRELOAD; POWER-UP RESET
  • HTS Code

    HTS (Harmonized Tariff Schedule) codes are product classification codes between 8-1 digits. The first six digits are an HS code, and the countries of import assign the subsequent digits to provide additional classification. U.S. HTS codes are 1 digits and are administered by the U.S. International Trade Commission.

    8542.39.00.01
  • Subcategory
    Programmable Logic Devices
  • Technology
    CMOS
  • Terminal Position
    DUAL
  • Terminal Form

    Occurring at or forming the end of a series, succession, or the like; closing; concluding.

    THROUGH-HOLE
  • Terminal Pitch

    The center distance from one pole to the next.

    2.54 mm
  • Reach Compliance Code
    not_compliant
  • Pin Count

    a count of all of the component leads (or pins)

    24
  • JESD-30 Code
    R-PDIP-T24
  • Number of Outputs
    10
  • Qualification Status

    An indicator of formal certification of qualifications.

    Not Qualified
  • Power Supplies

    an electronic circuit that converts the voltage of an alternating current (AC) into a direct current (DC) voltage.?

    5 V
  • Temperature Grade

    Temperature grades represent a tire's resistance to heat and its ability to dissipate heat when tested under controlled laboratory test conditions.

    COMMERCIAL EXTENDED
  • Max Supply Voltage

    In general, the absolute maximum common-mode voltage is VEE-0.3V and VCC+0.3V, but for products without a protection element at the VCC side, voltages up to the absolute maximum rated supply voltage (i.e. VEE+36V) can be supplied, regardless of supply voltage.

    5.25 V
  • Min Supply Voltage

    The minimum supply voltage (V min ) is explored for sequential logic circuits by statistically simulating the impact of within-die process variations and gate-dielectric soft breakdown on data retention and hold time.

    4.75 V
  • Nominal Supply Current

    Nominal current is the same as the rated current. It is the current drawn by the motor while delivering rated mechanical output at its shaft.

    135 mA
  • Propagation Delay

    the flight time of packets over the transmission link and is limited by the speed of light.

    15 ns
  • Architecture
    PLS-TYPE
  • Number of Inputs
    20
  • Organization
    10 DEDICATED INPUTS, 10 I/O
  • Seated Height-Max
    4.57 mm
  • Programmable Logic Type

    Generally, programmable logic devices can be described as being one of three different types: Simple programmable logic devices (SPLD) Complex programmable logic devices (CPLD) Field programmable logic devices (FPGA).

    EE PLD
  • Max Frequency
    75 MHz
  • Output Function

    An output function is a function that an optimization function calls at each iteration of its algorithm. Typically, you use an output function to generate graphical output, record the history of the data the algorithm generates, or halt the algorithm based on the data at the current iteration.

    MACROCELL
  • Number of Dedicated Inputs
    10
  • Number of Product Terms
    75
  • Width
    7.62 mm
  • Length
    31.855 mm
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