Intel Corporation EPM240M100I4N

Surface Mount

having leads that are designed to be soldered on the side of a circuit board that the body of the component is mounted on.

YES

Number of Terminals

100

Rohs Code

Yes

Part Life Cycle Code

Active

Ihs Manufacturer

INTEL CORP

Package Description

6 X 6 MM, 0.50 MM PITCH, LEAD FREE, MICRO, FBGA-100

Clock Frequency-Max

166.6 MHz

Number of I/O Lines

80

Operating Temperature-Max

100 °C

Operating Temperature-Min

-40 °C

Package Body Material

PLASTIC/EPOXY

Package Code

BGA

Package Equivalence Code

BGA100,11X11,20

Package Shape

SQUARE

Package Style

GRID ARRAY

Supply Voltage-Max

2.625 V

Supply Voltage-Min

2.375 V

Supply Voltage-Nom

2.5 V

JESD-609 Code

e1

Terminal Finish

TIN SILVER COPPER

Additional Feature

Any Feature, including a modified Existing Feature, that is not an Existing Feature.

IT CAN ALSO OPERATE AT 3.3V

HTS Code

HTS (Harmonized Tariff Schedule) codes are product classification codes between 8-1 digits. The first six digits are an HS code, and the countries of import assign the subsequent digits to provide additional classification. U.S. HTS codes are 1 digits and are administered by the U.S. International Trade Commission.

8542.39.00.01

Terminal Position

BOTTOM

Terminal Form

Occurring at or forming the end of a series, succession, or the like; closing; concluding.

BALL

Terminal Pitch

The center distance from one pole to the next.

0.5 mm

Reach Compliance Code

compliant

JESD-30 Code

S-PBGA-B100

Number of Outputs

80

Qualification Status

An indicator of formal certification of qualifications.

Not Qualified

Propagation Delay

the flight time of packets over the transmission link and is limited by the speed of light.

6.1 ns

Number of Inputs

80

Organization

0 DEDICATED INPUTS, 80 I/O

Programmable Logic Type

Generally, programmable logic devices can be described as being one of three different types: Simple programmable logic devices (SPLD) Complex programmable logic devices (CPLD) Field programmable logic devices (FPGA).

FLASH PLD

Output Function

An output function is a function that an optimization function calls at each iteration of its algorithm. Typically, you use an output function to generate graphical output, record the history of the data the algorithm generates, or halt the algorithm based on the data at the current iteration.

MACROCELL

Number of Macro Cells

192

JTAG BST

YES

In-System Programmable

YES

Length

6 mm

Width

6 mm