Cypress Semiconductor CY7C382A-1JC

Surface Mount

having leads that are designed to be soldered on the side of a circuit board that the body of the component is mounted on.

YES

Number of Terminals

68

Rohs Code

No

Part Life Cycle Code

Obsolete

Ihs Manufacturer

CYPRESS SEMICONDUCTOR CORP

Part Package Code

LCC

Package Description

PLASTIC, LCC-68

Clock Frequency-Max

242.5 MHz

Operating Temperature-Max

70 °C

Package Body Material

PLASTIC/EPOXY

Package Code

QCCJ

Package Equivalence Code

LDCC68,1.0SQ

Package Shape

SQUARE

Package Style

CHIP CARRIER

Supply Voltage-Max

5.25 V

Supply Voltage-Min

4.75 V

Supply Voltage-Nom

5 V

JESD-609 Code

e0

Terminal Finish

TIN LEAD

Additional Feature

Any Feature, including a modified Existing Feature, that is not an Existing Feature.

MAX. 56 I/OS; OTP BASED

HTS Code

HTS (Harmonized Tariff Schedule) codes are product classification codes between 8-1 digits. The first six digits are an HS code, and the countries of import assign the subsequent digits to provide additional classification. U.S. HTS codes are 1 digits and are administered by the U.S. International Trade Commission.

8542.39.00.01

Terminal Position

QUAD

Terminal Form

Occurring at or forming the end of a series, succession, or the like; closing; concluding.

J BEND

Terminal Pitch

The center distance from one pole to the next.

1.27 mm

Reach Compliance Code

not_compliant

Pin Count

a count of all of the component leads (or pins)

68

JESD-30 Code

S-PQCC-J68

Number of Outputs

56

Qualification Status

An indicator of formal certification of qualifications.

Not Qualified

Temperature Grade

Temperature grades represent a tire's resistance to heat and its ability to dissipate heat when tested under controlled laboratory test conditions.

COMMERCIAL

Number of Inputs

64

Organization

96 CLBS, 1000 GATES

Seated Height-Max

5.08 mm

Programmable Logic Type

Generally, programmable logic devices can be described as being one of three different types: Simple programmable logic devices (SPLD) Complex programmable logic devices (CPLD) Field programmable logic devices (FPGA).

FIELD PROGRAMMABLE GATE ARRAY

Combinatorial Delay of a CLB-Max

6.384 ns

Number of CLBs

96

Number of Logic Cells

An FPGA contains a large number of logic cells. Each logic cell can be configured to implement a certain set of functions. Each logic cell has a fixed number of inputs and outputs. Flip-flop can be incorporated into a multiplexer-based logic module to implement sequential logic.

96

Number of Equivalent Gates

1000

Length

24.2316 mm

Width

24.2316 mm