ALTERA 5M80ZE64C5N

Mounting Type

Surface Mount

Package / Case

64-TQFP Exposed Pad

Surface Mount

having leads that are designed to be soldered on the side of a circuit board that the body of the component is mounted on.

YES

Supplier Device Package

64-EQFP (7x7)

Number of Terminals

64

Manufacturer

ABB

Manufacturer Part Number

ACH580-BCR-017A-6+F267+K475+L501

Number of I/Os

54

Number of Macrocells

64

MSL

MSL 3 - 168 hours

Package Description

HTFQFP, TQFP64,.35SQ,16

Package Style

FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH

Moisture Sensitivity Levels

3

Package Body Material

PLASTIC/EPOXY

Package Equivalence Code

TQFP64,.35SQ,16

Supply Voltage-Nom

1.8 V

Reflow Temperature-Max (s)

NOT SPECIFIED

Supply Voltage-Min

1.71 V

Operating Temperature-Max

85 °C

Rohs Code

Yes

Clock Frequency-Max

118.3 MHz

Package Code

HTFQFP

Package Shape

SQUARE

Part Life Cycle Code

Active

Number of I/O Lines

54

Samacsys Description

ALTERA - 5M80ZE64C5N - IC, CPLD, MAX V, 80 LE, 64EQFP

Ihs Manufacturer

INTEL CORP

Supply Voltage-Max

1.89 V

Risk Rank

0.95

Operating Temperature

The operating temperature is the range of ambient temperature within which a power supply, or any other electrical equipment, operate in. This ranges from a minimum operating temperature, to a peak or maximum operating temperature, outside which, the power supply may fail.

0°C ~ 85°C (TJ)

Series

MAX® V

Packaging

Semiconductor package is a carrier / shell used to contain and cover one or more semiconductor components or integrated circuits. The material of the shell can be metal, plastic, glass or ceramic.

Tray

JESD-609 Code

e3

Part Status

Parts can have many statuses as they progress through the configuration, analysis, review, and approval stages.

Active

ECCN Code

EAR99

Terminal Finish

Matte Tin (Sn) - annealed

Additional Feature

Any Feature, including a modified Existing Feature, that is not an Existing Feature.

YES

HTS Code

HTS (Harmonized Tariff Schedule) codes are product classification codes between 8-1 digits. The first six digits are an HS code, and the countries of import assign the subsequent digits to provide additional classification. U.S. HTS codes are 1 digits and are administered by the U.S. International Trade Commission.

8542.39.00.01

Subcategory

Programmable Logic Devices

Technology

CMOS

Terminal Position

QUAD

Terminal Form

Occurring at or forming the end of a series, succession, or the like; closing; concluding.

GULL WING

Peak Reflow Temperature (Cel)

NOT SPECIFIED

Terminal Pitch

The center distance from one pole to the next.

0.4 mm

Reach Compliance Code

compliant

Frequency

118.3MHz

Base Part Number

5M80Z

JESD-30 Code

S-PQFP-G64

Qualification Status

An indicator of formal certification of qualifications.

Not Qualified

Power Supplies

an electronic circuit that converts the voltage of an alternating current (AC) into a direct current (DC) voltage.?

1.8,1.2/3.3 V

Temperature Grade

Temperature grades represent a tire's resistance to heat and its ability to dissipate heat when tested under controlled laboratory test conditions.

OTHER

Programmable Type

These include Field Programmable Logic Devices (FPGAs), Complex Programmable Logic Devices (CPLD) and Programmable Logic Devices (PLD, PLA, PAL, GAL). There are also devices that are the analog equivalent of these called field programmable analog arrays.

In System Programmable

Propagation Delay

the flight time of packets over the transmission link and is limited by the speed of light.

7.9ns

Organization

54 I/O

Seated Height-Max

1.2 mm

Programmable Logic Type

Generally, programmable logic devices can be described as being one of three different types: Simple programmable logic devices (SPLD) Complex programmable logic devices (CPLD) Field programmable logic devices (FPGA).

FLASH PLD

Output Function

An output function is a function that an optimization function calls at each iteration of its algorithm. Typically, you use an output function to generate graphical output, record the history of the data the algorithm generates, or halt the algorithm based on the data at the current iteration.

MACROCELL

Number of Macro Cells

64

JTAG BST

YES

Voltage Supply - Internal

1.71 V ~ 1.89 V

Delay Time tpd(1) Max

7.5ns

Number of Logic Elements/Blocks

80

In-System Programmable

YES

Width

7 mm

Length

7 mm